PRODUCT OVERVIEW
Infinior MicroSystems' IMS16N Spider®
is a network enhanced version of IMS16C.
In addition to IMS16C peripherals,
IMS16N microcontroller also has 10/100 Base-T MAC Control Unit, 3 UARTs, HDLC controller and 16 General Purpose Registers.
< Under development >
IMS16N is suitable for variety of networking applications including:
  • Internet appliances
  • PBX applications, digital phones, and key telephone system

  • Security installations, Industrial Control, Building Automation

  • Digital Set-top box, Cable modem

  • Medical Devices, Printers

  • Embedded Network Equipments

  • Remote Measurement Equipments

FEATURE
  Compatibility
  • 100% software compatible with x86/x88 (i80186/i80188)real mode

  • Supported by widely available native x86 development tools
    (e.g. MASM, TASM, …)

  Technology
  • Fully synchronous and static design

  • 100MHz operation in 3.3 Volt

  • 0.35um 3.3V static CMOS process

  • 3.3V I/O Pad (5V tolerant I/O)

  • 144-pin QFP (Quad Flat Package)
  Core
  • 100MHz operation with 3 cycle access (T1, T2, T3)

  • Byte/Word operation. (80186 mode, 80188 mode)

  • 16M Byte memory address space, 64K byte I/O space

  • Non-multiplexed 24-bit Address Bus

  • SDRAM address shares with Address bus

  • Two way set-associative 16KB instruction Cache
  Peripheral
  • Chip select

    • 1 Upper Memory Chip Select
      (Ending address is fixed at FFFFFh)

    • 1 Lower Memory Chip Select
      (Starting address is fixed at 00000h)

    • 6 Peripheral Chip Select
      (Block size is fixed at 256 bytes)

    • 4 Midrange Chip Select
      (Starting address and block size are programmable)

    • PCS and MCS Auxiliary
      (Affects both PCS and MCS)
  • Interrupt Control Unit

    • 6 External Interrupts
      5 Maskable Interrupts
      1 Non-Maskable Interrupts
    • 11 Internal Interrupts
      3 Timers
      2 DMA Channels
      3 UART Serial port
      1 HDLC controllers
      1 MAC controller
    • Supports Master Mode and Fully Nested Mode

    • Programmable Interrupt Priority
  • Timer Control Unit

    • Three 16 Bit Programmable Timers
         2 External Timers
         1 Internal Watch Dog Timer
  • DMA Control Unit

    • Shares Two high-speed DMA channels with UART serial port

    • Data transfer can occur between memory and I/O space

    • Two Bus cycles are necessary for each data transfer
  • MAC Control Unit

    • Support IEEE802.3/802.3u(10/100Mbps)

    • Internal FIFO and DMA operation

    • MII/7 wire PHY interface
  • 3 UART Serial Port Interface
    Full duplex operation
    7, 8-bit data transfer
    Odd parity, Even parity or No parity
    1 or 2 stop bits
    Loop back mode
    Ability to break character transmit
    • 2 UART port with DMA operation
    • 1 UART port with normal operation
  • 38 User Programmable I/O
  • SDRAM Control Unit
    • Support 4 Banks (512Kbytes each)
    • Support 2 Banks (960Kbytes each)
  • HDLC Control Unit
    • CRC-CCITT, CRC16, Two 64 Bytes FIFO/ch. Q921. LAPB
      and LAPD compliant
  • Sixteen 16-bit General Purpose Register
  • PLL Management Unit
    • 1/2, MD1(90.3MHz),MD2(100MHz),x6
  Software Development Environment
  • Startup code & Boot loader
  • Cross compiler(dev86, Borland C/C++,Visual C/C++,Locator,Paradigm..)
  • RTOS(Any x86 16bit core supporting OS)
  • Stacks(LAN driver(RTL8019,CS8900),IP/TCP,UDP/tFtp,Web Server,DHCP,ATA-4/FAT32 file system)
IMS16B
IMS16C
IMS16N
IMS5016E
DSP5
DSP2
IMS5016E
µ-Processor  (IMS16E )
DSP ( DSP5 , DSP2)
Peripherals
INTC
DMAC
KBDC
PCMCIAC
NTSC
LCD
I/F
SDRAMC
I²C Host/Target
UDC (v1.1 compilant)
PCI (v2.0 target device)
Adaptive Echo Canceller
Digital Filter Banks for 3GPP digital cell enhancer
Network throughput Enhancer
Embedded system
Router
IXR
IAR
Internet STB (Set-Top-Box)
Web based Internet appliance
VoIP Gateway solution
S/W
Linux,RTOS,Zudra,TCP/IP stack...
                                   
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