Infinior Microsystems’ DSP5® is a high performance 16-bit fixed point digital signal processor core IP. This is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor core provides an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals.DSP5® also provides a highly specialized instruction set, which is the basis of the operational flexibility and speed of DSP.

DSP5®is designed and prepared to be used as an ASIC library element in variety of DSP applications and SOC design. This core approach gives both operational flexibility and numerical capability to the SOC designer.

The DSP5® core is proven at 0.35um static CMOS integrated-circuit technology. It is designed to execute more than 70 MIPS.

• 40-bit Arithmetic Logic Unit including One Barrel Shifter
  and Two independent 40-bit Accumulators
• 17 x 17 Parallel Multiplier Coupled to a 40-bit dedicated
  Adder
• Compare Select and Store Unit, Exponent Encoder in a
  Single Cycle
• Two Address Generators with Eight Auxiliary Registers
  and Two Auxiliary Register Arithmetic Units
• Instruction with 32-bit Long Word Operand
• Arithmetic Instruction with Parallel Store and Parallel Load
• 6 Stage Pipe-line
  (Pre-fetch, Fetch, Decoder, Access, Read, Execute)
• Supports easy of use design Environment
  (VHDL/Verilog/FPGA Netlist/ASIC Netlist with Simulation Codes and Vectors)

• Multi-standard Audio CODEC i.e. MP3, WMA, AC3 etc.
• VoIP Voice processor i.e. G.729, G.723.1 etc.
• Modem data pump i.e. ITU-T V.34, G.DMT, G.VDSL ...
• Speech recognition and synthesis
• Echo cancellation