/* // Processor definition file for the Infinior MicroSystem IMS16C microprocessor // Copyright (C) 2002 Infinior MicroSystems co., ltd. All rights reserved. // // This file contains defintions for manipulating the Infinior MicroSystem IMS16C // microprocessor peripheral control block. These definitions are for // I/O mapped peripheral registers. */ #if !defined(_IMS16C_H) #define _IMS16C_H /* // Check that the required symbols are defined */ #if !defined(IOB16C) #error Must define the IMS16C I/O base address #endif /* // Peripheral Control Block register offsets and definitions */ /* Peripheral Control Block Relocation Register */ #define RELREG IOB16C + 0xFE /* Relocation Register */ #define RELREG_S_M 0x4000 /* Slave-Master mode */ #define RELREG_M_IO 0x1000 /* Memory-IO Space */ /* Processor Release Level Register */ #define PRL IOB16C + 0xF4 /* Not yet defined */ /* HDLC Registers */ #define HDCTR0 IOB16C + 0xBE /* HDLC0 Control Reg */ #define HDSTR0 IOB16C + 0xBC /* HDLC0 Status Reg */ #define TXBFR0 IOB16C + 0xBA /* HDLC0 Transmit Buf Reg */ #define RXBFR0 IOB16C + 0xB8 /* HDLC0 Receive Buf Reg */ #define BDREG0 IOB16C + 0xB6 /* HDLC0 Baud Clk Setting Reg */ #define HDCTR1 IOB16C + 0xB4 /* HDLC1 Control Reg */ #define HDSTR1 IOB16C + 0xB2 /* HDLC1 Status Reg */ #define TXBFR1 IOB16C + 0xB0 /* HDLC1 Transmit Buf Reg */ #define RXBFR1 IOB16C + 0xAE /* HDLC1 Receive Buf Reg */ #define RDREG1 IOB16C + 0xAC /* HDLC1 Baud Clk Setting Reg */ //------ HDCTR0, HDCTR1 Mask ------------------------------------------------// #define TX_INT_EN 0x8000 /* TX INT Enable mask */ #define TX_INT_SEL 0x6000 /* TX INT Src Select mask */ #define RX_INT_EN 0x0800 /* RX INT Evable mask */ #define RX_INT_SEL 0x0400 /* RX INT Src Select mask */ #define RX_ERR_INT_EN 0x0100 /* RX Err INT Enable mask */ #define TX_CLK_EN 0x0080 /* TX Internal Clk Src Enable mask */ #define RX_CLK_EN 0x0040 /* RX Internal clk src Enable mask */ #define CRC_SEL 0x0004 /* CRC selection mask */ #define TX_ABORT_EN 0x0002 /* TX Data Abort Enable mask */ #define TX_START_EN 0x0001 /* TX Start Enable mask */ //------ HDSTR0, HDSTR1 Mask ------------------------------------------------// #define TX_EMPTY 0x8000 /* TX FIFO Empty mask */ #define TX_ALMOST_FULL 0x4000 /* TX FIFO Almost Full mask */ #define TX_HALF_FULL 0x2000 /* TX FIFO Half Full mask */ #define TX_FULL 0x1000 /* TX FIFO Full mask */ #define TX_ABORT 0x0800 /* TX Data Abort mask */ #define TX_TRANSMITTING 0x0400 /* TX Data is being Transmitting mask */ #define RX_OVERRUN 0x0100 /* RX Data FIFO Push Error mask */ #define RX_EMPTY 0x0080 /* RX FIFO Empty mask */ #define RX_ALMOST_EMPTY 0x0040 /* RX FIFO Almost Empty mask */ #define RX_HALF_FULL 0x0020 /* RX FIFO Half Full mask */ #define RX_FULL 0x0010 /* RX FIFO Full mask */ #define RX_ABORT 0x0004 /* RX Data Abort mask */ #define RX_FRAME_ERROR 0x0002 /* RX Frame Error mask */ #define RX_FCS_ERROR 0x0001 /* RX Frame Check Sequence Error mask */ #define RX_EOF 0x0000 /* RX End of Frame mask */ //------ TXBFR0, TXBFR1 Mask ------------------------------------------------// #define TX_Data_Buf_mask 0x00FF /* TX Data buffer mask */ //------ RXBFR0, RXBFR1 Mask ------------------------------------------------// #define RX_Data_Buf_mask 0x00FF /* RX Data buffer mask */ /*--- RDREG0, RDREG1 should be same with DIV0 which is defined beforehand */ /* at the last part of this file. -------------------------*/ /* i.e. Let RDREG0 = DIV0 or RDREG1 = DIV0 */ /* Power Save Control Register */ #define PDCON IOB16C + 0xF0 /* PDCON Register */ #define PDCON_PSEN 0x8000 /* Enable Power-Save Mode Mask */ #define PDCON_CBF 0x0800 /* PDCON CBF mask */ #define PDCON_CBD 0x0400 /* PDCON CBD mask */ #define PDCON_CAF 0x0200 /* PDCON CAF mask */ #define PDCON_CAD 0x0100 /* PDCON CAD mask */ #define PDCON_F2 0x0004 /* PDCON F2 mask */ #define PDCON_F1 0x0002 /* PDCON F1 mask */ #define PDCON_F0 0x0001 /* PDCON F0 mask */ /* SDRAM Controller Mode Set Register */ #define SDMODE IOB16C + 0xEE /* SDRAM Controller Mode Set Register */ #define SDMODE_WBL 0x0200 /* SDRAM Burst Mode Disable Mask */ #define SDMODE_TM 0x0100 /* SDRAM Test Mode Disable Mask */ #define SDMODE_CAS2 0x0020 /* SDRAM CAS Latency 2 Set Mask */ #define SDMODE_CAS3 0x0040 /* SDRAM CAS Latency 3 Set Mask */ #define SDMODE_BT 0x0008 /* SDRAM Interleave Burst Type Set Mask */ #define SDMODE_BL2 0x0001 /* SDRAM Burst Length 2 Set Mask */ #define SDMODE_BL4 0x0002 /* SDRAM Burst Length 4 Set Mask */ #define SDMODE_BL8 0x0004 /* SDRAM Burst Length 8 Set Mask */ /* SDRAM Controller Auto Refresh Duty Cycle Register */ #define SDDUTY IOB16C + 0xEC /* Refresh Cycle = Refresh Time / (ROW LINE * Main Clock duration) */ /* SDRAM Controller Enable Register */ #define SDEN IOB16C + 0xEA /* SDRAM Controller Enable Register */ #define SDEN_EN 0x0001 /* SDRAM Controller Enable Mask */ /* Enhanced Mode Control Registers */ #define EDRAM IOB16C + 0xE4 /* Enable RCU Register */ #define CDRAM IOB16C + 0xE2 /* Clock Prescaler Register */ #define MDRAM IOB16C + 0xE0 /* Memory Partition Register */ /* DMA Register Definitions */ #define D0CON IOB16C + 0xCA /* DMA0 Control Register */ #define D1CON IOB16C + 0xDA /* DMA1 Control Register */ #define DCON_DMIO 0x8000 /* Destination Address Space Select */ #define DCON_DDEC 0x4000 /* Destination Decrement */ #define DCON_DINC 0x2000 /* Destination Increment */ #define DCON_SMIO 0x1000 /* Source Address Space Select */ #define DCON_SDEC 0x0800 /* Source Decrement */ #define DCON_SINC 0x0400 /* Source Increment */ #define DCON_TC 0x0200 /* Termnial Count */ #define DCON_INT 0x0100 /* Interrupt */ #define DCON_SYN1 0x0080 /* Synchronzation Type1 */ #define DCON_SYN0 0x0040 /* Synchronzation Type0 */ #define DCON_P 0x0020 /* Relative Priority */ #define DCON_TDRQ 0x0010 /* Timer Enalbe-Disable Request */ #define DCON_CHG 0x0004 /* Change Start Bit */ #define DCON_ST 0x0002 /* Start-Stop DMA Channel */ #define DCON_BW 0x0001 /* Byte-Word Select */ #define D0TC IOB16C + 0xC8 /* DMA0 Transfer Count Register */ #define D1TC IOB16C + 0xD8 /* DMA1 Transfer Count Register */ #define D0DSTH IOB16C + 0xC6 /* DMA0 Destination High Register */ #define D0DSTL IOB16C + 0xC4 /* DMA0 Destination Low Register */ #define D0SRCH IOB16C + 0xC2 /* DMA0 Source High Register */ #define D0SRCL IOB16C + 0xC0 /* DMA0 Source Low Register */ #define D1DSTH IOB16C + 0xD6 /* DMA1 Destination High Register */ #define D1DSTL IOB16C + 0xD4 /* DMA1 Destination Low Register */ #define D1SRCH IOB16C + 0xD2 /* DMA1 Source High Register */ #define D1SRCL IOB16C + 0xD0 /* DMA1 Source Low Register */ /* Chip Select Register Definitions */ #define UMCS IOB16C + 0xA0 /* UMCS Register */ #define LMCS IOB16C + 0xA2 /* LMCS Register */ #define MPCS IOB16C + 0xA8 /* MPCS Register */ #define MMCS IOB16C + 0xA6 /* MMCS Register */ #define PACS IOB16C + 0xA4 /* PACS Register */ /* Uart Control Register Definitions */ #define U0CT IOB16C + 0x80 /* Serial Port Control Register */ #define U1CT IOB16C + 0x8C /* Serial Port Control Register */ #define U2CT IOB16C + 0x96 /* Serial Port Control Register */ #define UCT_TXIE 0x0800 /* THREIE TX Int Enable mask */ #define UCT_RXIE 0x0400 /* RDRIE RX Int Enable mask */ #define UCT_LOOP 0x0200 /* Loopback */ #define UCT_BRK 0x0100 /* Send Break */ #define UCT_BRKVAL 0x0080 /* Break Value */ #define UCT_PMODE0 0x0040 /* Parity Mode 0 */ #define UCT_PMODE1 0x0020 /* Parity Mode 1 */ #define UCT_PMODE_NONE 0x0000 /* No Parity mask */ #define UCT_PMODE_ODD UCT_PMODE0 /* ODD Parity mask */ #define UCT_PMODE_EVEN UCT_PMODE0|UCT_PMODE1 /* EVEN Parity mask */ #define UCT_WLGN 0x0010 /* Word Length */ #define UCT_WLGN_8BIT 0x0010 /* 8 Bit word mask */ #define UCT_WLGN_7BIT 0x0000 /* 7 Bit word mask */ #define UCT_STP 0x0008 /* Stop Bits */ #define UCT_STP_2STOP UCT_STP /* 2 Stop bits mask */ #define UCT_STP_1STOP 0x0000 /* 1 Stop bits mask */ #define UCT_TMODE 0x0004 /* TMODE enable mask */ #define UCT_RSIE 0x0002 /* RSIE mask (generate int on err) */ #define UCT_RMODE 0x0001 /* RMODE mask (Rcv interrupt mode) */ #define UCT_D0 0x0002 #define UCT_D1 0x0004 #define UCT_D2 0x0008 #define UCT_NODMA 0x0000 /* NO DMA */ #define UCT_R0T1 0x2000 /* Recv => DMA0, Trns => DMA1 */ #define UCT_R1T0 0x4000 /* Recv => DMA1, Trns => DMA0 */ #define UCT_RSVD 0x6000 /* Reserved */ #define UCT_R0TN 0x8000 /* Recv => DMA0, Trns => No DMA */ #define UCT_R1TN 0xA000 /* Recv => DMA1, Trns => No DMA */ #define UCT_RNT0 0xC000 /* Recv => No DMA, Trns => DMA0 */ #define UCT_RNT1 0xE000 /* Recv => No DMA, Trns => DMA1 */ /* Serial Port Status Register Definitions */ #define U0STS IOB16C + 0x82 /* Serial Port Status Register */ #define U1STS IOB16C + 0x8E /* Serial Port Status Register */ #define U2STS IOB16C + 0x98 /* Serial Port Status Register */ #define USTS_TEMT 0x0040 /* Transmit Shift Reg Empty mask*/ #define USTS_THRE 0x0020 /* Transmit Hold Reg Empty mask */ #define USTS_RDR 0x0010 /* Receive Data Ready mask */ #define USTS_BRKI 0x0008 /* Break Interrupt mask */ #define USTS_FER 0x0004 /* Framing Error mask */ #define USTS_PER 0x0002 /* Parity Error mask */ #define USTS_OER 0x0001 /* Overrun Error mask */ /*********************************************************/ /* Serial Port Control Register(SPCT, Offset 80h) */ /* _____________________________________________________ */ /* |D2|D1|D0|TX|RX|LO|BR|BRK|PMO|PMO|WLG|STP|TMO|RSI|RM |*/ /* | | | |IE|IE|OP|K |VAL|DE1|DE0|N | |DE |E |ODE|*/ /* ----------------------------------------------------- */ /*********************************************************/ #define UCT_NODMA 0x0000 #define UCT_R0T1 0x2000 #define UCT_R1T0 0x4000 #define UCT_RSVD 0x6000 #define UCT_R0TN 0x8000 #define UCT_R1TN 0xA000 #define UCT_RNT0 0xC000 #define UCT_RNT1 0xE000 /* Serial Port Transmit Data */ #define U0TD IOB16C + 0x84 #define U1TD IOB16C + 0x90 #define U2TD IOB16C + 0x9A /* Serial Port Receive Data */ #define U0RD IOB16C + 0x86 #define U1RD IOB16C + 0x92 #define U2RD IOB16C + 0x9C /* Serial Port Baud Rate Divisor */ #define U0BAUD IOB16C + 0x88 /* Xtal / (BDIV+1) / 32 = Baud */ #define U1BAUD IOB16C + 0x94 /* Xtal / (BDIV+1) / 32 = Baud */ #define U2BAUD IOB16C + 0x9E /* Xtal / (BDIV+1) / 32 = Baud */ /* Define pin modes for serial port */ #define SER_PIOMODE 0xe7ff #define SER_PIODIR 0xe7ff /* PIO Register Definitions */ #define PIOMODE0 IOB16C + 0x70 /* PIO 0 Mode Register */ #define PDIR0 IOB16C + 0x72 /* PIO 0 Direction Register */ #define PDATA0 IOB16C + 0x74 /* PIO 0 Data Register */ #define PIOMODE1 IOB16C + 0x76 /* PIO 1 Mode Register */ #define PDIR1 IOB16C + 0x78 /* PIO 1 Direction Register */ #define PDATA1 IOB16C + 0x7A /* PIO 1 Data Register */ #define PIOMODE2 IOB16C + 0x6A /* PIO 2 Mode Register */ #define PDIR2 IOB16C + 0x6C /* PIO 2 Direction Register */ #define PDATA2 IOB16C + 0x6E /* PIO 2 Data Register */ /* Interrupt Type */ #define DIV_ERR 0x00 /* Divide Error Exception */ #define TRACE_INT 0x01 /* Trace Interrupt */ #define NMI 0x02 /* Non-Maskable Inerrupt(NMI) */ #define BRKP 0x03 /* Breakpoint Interrupt */ #define INT0_OVF 0x04 /* INT0 Detected Overflow Exception */ #define ARRY_BNDS 0x05 /* Array Bounds Exception */ #define UNUSED_OPCODE 0x06 /* Unused Opcode Exception */ #define ESC_OPCODE 0x07 /* ESC Opcode Exception */ #define TIMER0 0x08 /* Timer0 Interrupt */ #define TIMER1 0x12 /* Timer1 Interrupt */ #define TIMER2 0x13 /* Timer2 Interrupt */ #define DMA0 0x0A /* DMA0 Interrupt */ #define DMA1 0x0B /* DMA1 Interrupt */ #define INT0 0x0C /* INT0 Interrupt */ #define INT1 0x0D /* INT1 Interrupt */ #define INT2 0x0E /* INT2 Interrupt */ #define INT3 0x0F /* INT3 Interrupt */ #define INT4 0x10 /* INT4 Interrupt */ #define WDT 0x11 /* Watchdog Timer Interrupt */ #define UART0 0x14 /* UART0 Serial Port Interrupt */ #define UART1 0x15 /* UART1 Serial Port Interrupt */ #define UART2 0x16 /* UART2 Serial Port Interrupt */ /* Interrupt Control Register Definitions */ /* Interrupt EOI Register Definitions */ #define EOI IOB16C + 0x22 /* End-of Interrupt Register */ #define EOI_NSPEC 0x8000 /* Non-Specific EIO */ // ---------------------------------------------- // EOI Type -- Delete or ? // ---------------------------------------------- #define EOI_TIMER0 TIMER0 #define EOI_TIMER1 TIMER1 #define EOI_TIMER2 TIMER2 #define EOI_DMA0 DMA0 #define EOI_DMA1 DMA1 #define EOI_INT0 INT0 #define EOI_INT1 INT1 #define EOI_INT2 INT2 #define EOI_INT3 INT3 #define EOI_INT4 INT4 #define EOI_WDT WDT #define EOI_UART0 UART0 #define EOI_UART1 UART1 #define EOI_UART2 UART2 #define POLL IOB16C + 0x24 /* Poll Register */ #define POLLST IOB16C + 0x26 /* Poll Status Register */ #define IMASK IOB16C + 0x28 /* Interrupt Mask Register */ #define IMASK_UART2 0x1000 /* Interrupt Mask for UART2 */ #define IMASK_UART1 0x0800 /* Interrupt Mask for UART1 */ #define IMASK_UART0 0x0400 /* Interrupt Mask for UART0 */ #define IMASK_WDT 0x0200 /* Interrupt Mask for WDT */ #define IMASK_I4 0x0100 /* Interrupt Mask for INT4 */ #define IMASK_I3 0x0080 /* Interrupt Mask for INT3 */ #define IMASK_I2 0x0040 /* Interrupt Mask for INT2 */ #define IMASK_I1 0x0020 /* Interrupt Mask for INT1 */ #define IMASK_I0 0x0010 /* Interrupt Mask for INT0 */ #define IMASK_D1 0x0008 /* Interrupt Mask for DMA1 */ #define IMASK_D0 0x0004 /* Interrupt Mask for DMA0 */ #define IMASK_TMR 0x0001 /* Interrupt Mask for Timer */ #define PRIMSK IOB16C + 0x2A /* Priority Mask Register */ #define PRIMSK_PRM2 0x0004 /* Priority Field Mask 2 */ #define PRIMSK_PRM1 0x0002 /* Priority Field Mask 1 */ #define PRIMSK_PRM0 0x0001 /* Priority Field Mask 0 */ #define PRIMSK_PRI0 0x0000 /* Priority 0 */ #define PRIMSK_PRI1 PRIMSK_PRM0 /* Priority 1 */ #define PRIMSK_PRI2 PRIMSK_PRM1 /* Priority 2 */ #define PRIMSK_PRI3 PRIMSK_PRM1|PRIMSK_PRM0 /* Priority 3 */ #define PRIMSK_PRI4 PRIMSK_PRM2 /* Priority 4 */ #define PRIMSK_PRI5 PRIMSK_PRM2|PRIMSK_PRM0 /* Priority 5 */ #define PRIMSK_PRI6 PRIMSK_PRM2|PRIMSK_PRM1 /* Priority 6 */ #define PRIMSK_PRI7 PRIMSK_PRM2|PRIMSK_PRM1|PRIMSK_PRM0 /*Priority 7*/ #define INSERV IOB16C + 0x2C /* In-service Register */ #define REQST IOB16C + 0x2E /* Interrupt Requset Register */ #define REQST_UART2 0x1000 /* Interrupt Reguest for UART2 */ #define REQST_UART1 0x0800 /* Interrupt Reguest for UART1 */ #define REQST_UART0 0x0400 /* Interrupt Reguest for UART0 */ #define REQST_WDT 0x0200 /* Interrupt Reguest for WDT */ #define REQST_I4 0x0100 /* Interrupt Reguest for INT4 */ #define REQST_I3 0x0080 /* Interrupt Reguest for INT3 */ #define REQST_I2 0x0040 /* Interrupt Reguest for INT2 */ #define REQST_I1 0x0020 /* Interrupt Reguest for INT1 */ #define REQST_I0 0x0010 /* Interrupt Reguest for INT0 */ #define REQST_D1 0x0008 /* Interrupt Reguest for DMA1 */ #define REQST_D0 0x0004 /* Interrupt Reguest for DMA0 */ #define REQST_TMR 0x0001 /* Interrupt Reguest for Timer */ #define INTSTS IOB16C + 0x30 /* Interrupt Status Register */ #define TCUCON IOB16C + 0x32 /* Timer Interrupt Control Register */ #define TCUCON_MSK 0x0008 #define TCUCON_PR2 0x0004 #define TCUCON_PR1 0x0002 #define TCUCON_PR0 0x0001 #define DMA0CON IOB16C + 0x34 /* DMA0 Interrupt Control Register */ #define DMA0CON_MSK 0x0008 #define DMA0CON_PR2 0x0004 #define DMA0CON_PR1 0x0002 #define DMA0CON_PR0 0x0001 #define DMA1CON IOB16C + 0x36 /* DMA1 Interrupt Control Register */ #define DMA1CON_MSK 0x0008 #define DMA1CON_PR2 0x0004 #define DMA1CON_PR1 0x0002 #define DMA1CON_PR0 0x0001 /* UART Serial Interrupt Control Registers */ #define U0CON IOB16C + 0x44 /* UART0 INT Control Register */ #define U1CON IOB16C + 0x46 /* UART1 INT Control Register */ #define U2CON IOB16C + 0x48 /* UART2 INT Control Register */ #define UCON_MSK 0x0008 /* MASK */ #define UCON_PR2 0x0004 /* Priority Level Mode 2 */ #define UCON_PR1 0x0002 /* Priority Level Mode 1 */ #define UCON_PR0 0x0001 /* Priority Level Mode 0 */ /*-----------------------------------------*/ /* INT0 and INT1 COntrol Registers */ #define I0CON IOB16C + 0x38 /* INT0 Control Register */ #define I1CON IOB16C + 0x3A /* INT1 Control Register */ /*-----------------------------------------*/ /* INT2 and INT3 COntrol Registers */ #define I2CON IOB16C + 0x3C /* INT2 Control Register */ #define I3CON IOB16C + 0x3E /* INT3 Control Register */ #define I4CON IOB16C + 0x40 /* INT4 Control Register */ #define ICON_SFNM 0x0040 /* Special Fully Nested Mode (I0CON&I1CON Only)*/ #define ICON_C 0x0020 /* Cascade Mode (I0CON&I1CON Only)*/ #define ICON_LTM 0x0010 /* Level Triggered Mode */ #define ICON_MSK 0x0008 /* MASK */ #define ICON_PR2 0x0004 /* Priority Level Mode 2 */ #define ICON_PR1 0x0002 /* Priority Level Mode 1 */ #define ICON_PR0 0x0001 /* Priority Level Mode 0 */ /*-----------------------------------------*/ /* Watchdog Timer Interupt Control Register */ #define WDCON IOB16C + 0x42 #define WDCON_MSK 0x0008 /* MASK */ #define WDCON_PR2 0x0004 /* Priority Level Mode 2 */ #define WDCON_PR1 0x0002 /* Priority Level Mode 1 */ #define WDCON_PR0 0x0001 /* Priority Level Mode 0 */ /*-----------------------------------------*/ /* Timer 0 and Timer 1 Mode and Control Registers */ #define T0CON IOB16C + 0x56 #define T1CON IOB16C + 0x5E #define T2CON IOB16C + 0x66 #define TCON_EN 0x8000 /* Enable Bit */ #define TCON_INH 0x4000 /* Inhibit Bit */ #define TCON_INT 0x2000 /* Interrupt Bit */ #define TCON_RIU 0x1000 /* Register in Use Bit(T0CON&T1CON only) */ #define TCON_MC 0x0020 /* Maximum Count bit */ #define TCON_RTG 0x0010 /* Retrigger Bit (T0CON&T1CON only) */ #define TCON_P 0x0008 /* Prescaler Bit (T0CON&T1CON only) */ #define TCON_EXT 0x0004 /* External Clock Bit(T0CON&T1CON only) */ #define TCON_ALT 0x0002 /* Alternate Compare Bit(T0CON&T1CON only)*/ #define TCON_CONT 0x0001 /* Continuous Mode Bit */ /*-----------------------------------------*/ #define T0CMPB IOB16C + 0x54 /* TMR0 Compare-B Register */ #define T0CMPA IOB16C + 0x52 /* TMR0 Compare-A Register */ #define T0CNT IOB16C + 0x50 /* TMR0 Count Register */ #define T1CMPB IOB16C + 0x5C /* TMR1 Compare-B Register */ #define T1CMPA IOB16C + 0x5A /* TMR1 Compare-A Register */ #define T1CNT IOB16C + 0x58 /* TMR1 Count Register */ #define T2CMPA IOB16C + 0x62 /* TMR2 Compare-A Register */ #define T2CNT IOB16C + 0x60 /* TMR2 Count Register */ /*-----------------------------------------*/ /* General Purpose Register 0~15 */ #define GPR0 IOB16C + 0x00 /* General Purpose Register 0 */ #define GPR1 IOB16C + 0x02 /* General Purpose Register 1 */ #define GPR2 IOB16C + 0x04 /* General Purpose Register 2 */ #define GPR3 IOB16C + 0x06 /* General Purpose Register 3 */ #define GPR4 IOB16C + 0x08 /* General Purpose Register 4 */ #define GPR5 IOB16C + 0x0A /* General Purpose Register 5 */ #define GPR6 IOB16C + 0x0C /* General Purpose Register 6 */ #define GPR7 IOB16C + 0x0E /* General Purpose Register 7 */ #define GPR8 IOB16C + 0x10 /* General Purpose Register 8 */ #define GPR9 IOB16C + 0x12 /* General Purpose Register 9 */ #define GPR10 IOB16C + 0x14 /* General Purpose Register 10 */ #define GPR11 IOB16C + 0x16 /* General Purpose Register 11 */ #define GPR12 IOB16C + 0x18 /* General Purpose Register 12 */ #define GPR13 IOB16C + 0x1A /* General Purpose Register 13 */ #define GPR14 IOB16C + 0x1C /* General Purpose Register 14 */ #define GPR15 IOB16C + 0x1E /* General Purpose Register 15 */ /*-----------------------------------------*/ /* // // Calculate the baud rate generator values // */ #if defined(BAUD) && defined(CLK) #if !(defined(MSC51) || defined(MSC60)) /* First, compute BAUD rate divisor */ #define DIV0 (CLK/BAUD/32)-1 /* BAUD = CLK/(DIV+1)/32 */ #define DIV1 (DIV0 + 1) /* Round up */ /* compute actual baud for both divisors */ #define BAUD0 (CLK/(DIV0+1)/32) #define BAUD1 (CLK/(DIV1+1)/32) /* Compare errors and choose better */ #if (BAUD0 - BAUD) < (BAUD - BAUD1) #define BAUDDIV DIV0 #define RATE_ERR (((BAUD0 - BAUD) * 100) / BAUD) #else #define BAUDDIV DIV1 #define RATE_ERR (((BAUD - BAUD1) * 100) / BAUD) #endif /* Test that the resulting error is acceptable */ #if ( RATE_ERR > 5 ) #error Greater than 5% Baudrate error try changing BAUD or CLK. #endif /* Baud rate error check */ #else /* MSC 5.1 and MSC 6.0 can't handle the computation */ /* You must manually determine BAUDDIV and assign it on the next line */ /* use the formula BAUDDIV = (CLK/BAUD/32)-1 */ #define BAUDDIV 0 #if (BAUDDIV==0) #error When using MSC 5.1 or MSC 6.0, you must compute BAUDDIV #endif #endif /* !(defined(MSC51) || defined(MSC60)) */ #endif /* defined(BAUD) && defined(CLK) */ #if (defined(NSEC) && defined(CLK)) #define CLKCNT CLK/4000000L*NSEC //#else //#error CLK or NSEC is not defined #endif /* defined(NSEC) && defined(CLK) */ #endif /* _IMS16C_H */