/*
//		Processor definition file for the Infinior MicroSystem IMS16B microprocessor
//		Copyright (C) 2001, 2002 Infinior MicroSystems co., ltd.  All rights reserved.
//
//		This file contains defintions for manipulating the Infinior MicroSystem IMS16B
//		microprocessor peripheral control block.  These definitions are for
//		I/O mapped peripheral registers.
*/

#if	!defined(_IMS16B_H)
#define	_IMS16B_H

/*
//		Check that the required symbols are defined
*/

#if	!defined(IOB16B)
#error	Must define the IMS16B I/O base address
#endif


/*
//		Peripheral Control Block register offsets and definitions
*/

/* Peripheral Control Block Relocation Register */
#define	RELREG		IOB16B + 0xFE	/* Relocation Register */


/* Power Save Control Register */
#define	PDCON		IOB16B + 0xF0	/* PDCON Register */
#define	PDCON_PSEN	0x8000		/* Enable Poer-Save Mode Mask */
#define	PDCON_CBF	0x0800		/* PDCON CBF mask */
#define	PDCON_CBD	0x0400		/* PDCON CBD mask */
#define	PDCON_CAF	0x0200		/* PDCON CAF mask */
#define	PDCON_CAD	0x0100		/* PDCON CAD mask */
#define	PDCON_F2	0x0004		/* PDCON F2 mask */
#define	PDCON_F1	0x0002		/* PDCON F1 mask */
#define	PDCON_F0	0x0001		/* PDCON F0 mask */

/* SDRAM Controller Mode Set Register */
#define	SDMODE		IOB16B + 0xEE		/* SDRAM Controller Mode Set Register */
#define SDMODE_WBL	0x0200		/* SDRAM Burst Mode Disable Mask */
#define SDMODE_TM	0x0100 		/* SDRAM Test Mode Disable Mask */
#define SDMODE_CAS2	0x0020		/* SDRAM CAS Latency 2 Set Mask */
#define SDMODE_CAS3	0x0040		/* SDRAM CAS Latency 3 Set Mask */
#define SDMODE_BT	0x0008		/* SDRAM Interleave Burst Type Set Mask */
#define SDMODE_BL2	0x0001		/* SDRAM Burst Length 2 Set Mask */
#define SDMODE_BL4	0x0002		/* SDRAM Burst Length 4 Set Mask */
#define SDMODE_BL8	0x0004		/* SDRAM Burst Length 8 Set Mask */

/* SDRAM Controller Auto Refresh Duty Cycle Register */
#define SDDUTY		IOB16B + 0xEC
/* Refresh Cycle = Refresh Time / (ROW LINE * Main Clock duration) */

/* SDRAM Controller Enable Register */
#define SDEN		IOB16B + 0xEA 	/* SDRAM Controller Enable Register */
#define SDEN_CON	0x0001		/* SDRAM Controller Enable Mask */

/* Enhanced Mode Control Registers */
#define	MDRAM		IOB16B + 0xE0	/* MDRAM Register */
#define	CDRAM		IOB16B + 0xE2	/* CDRAM Register */
#define	EDRAM		IOB16B + 0xE4	/* EDRAM Register */


/* DMA Register Definitions */
#define	D0CON		IOB16B + 0xCA	/* DMA0 Control Register */
#define	D0TC		IOB16B + 0xC8	/* DMA0 Transfer Count Register */
#define	D0DSTH		IOB16B + 0xC6	/* DMA0 Destination High Register */
#define	D0DSTL		IOB16B + 0xC4	/* DMA0 Destination Low  Register */
#define	D0SRCH		IOB16B + 0xC2	/* DMA0 Source High Register */
#define	D0SRCL		IOB16B + 0xC0	/* DMA0 Source Low  Register */

#define	D1CON		IOB16B + 0xDA	/* DMA1 Control Register */
#define	D1TC		IOB16B + 0xD8	/* DMA1 Transfer Count Register */
#define	D1DSTH		IOB16B + 0xD6	/* DMA1 Destination High Register */
#define	D1DSTL		IOB16B + 0xD4	/* DMA1 Destination Low  Register */
#define	D1SRCH		IOB16B + 0xD2	/* DMA1 Source High Register */
#define	D1SRCL		IOB16B + 0xD0	/* DMA1 Source Low  Register */

/* DMA Control Register */
#define DCON_DMIO   	0x8000
#define DCON_DDEC   	0x4000
#define DCON_DINC   	0x2000
#define DCON_SMIO   	0x1000
#define DCON_SDEC   	0x0800
#define DCON_SINC   	0x0400
#define DCON_TC     	0x0200
#define DCON_INT    	0x0100
#define DCON_SYN1   	0x0080
#define DCON_SYN0   	0x0040
#define DCON_P      	0x0020
#define DCON_TDRQ   	0x0010
#define DCON_CHG    	0x0004
#define DCON_ST     	0x0002
#define DCON_BW     	0x0001

/* Chip Select Register Definitions */
#define	UMCS		IOB16B + 0xA0	/* UMCS Register */
#define	LMCS		IOB16B + 0xA2	/* LMCS Register */
#define	MPCS		IOB16B + 0xA8	/* MPCS Register */
#define	MMCS		IOB16B + 0xA6	/* MMCS Register */
#define	PACS		IOB16B + 0xA4	/* PACS Register */


/* Serial Port Control Register Definitions */
#define	SPCT		IOB16B + 0x80	/* Serial Port Control Register */

#define	SER_THREIE	0x0800		/* THREIE TX Int Enable mask */
#define	SER_RDRIE	0x0400		/* RDRIE RX Int Enable mask */
#define	SER_LOOP	0x0200		/* Loopback */
#define	SER_BRK		0x0100		/* Send Break */
#define	SER_BRKVAL	0x0080		/* Break Value */
#define	SER_NPARITY	0x0000		/* No parity mask */
#define	SER_OPARITY	0x0040		/* Odd parity mask */
#define	SER_EPARITY	0x0060		/* Even parity mask */
#define	SER_8BIT	0x0010		/* 8 Bit word mask */
#define	SER_7BIT	0x0000		/* 7 Bit word mask */
#define	SER_2STOP	0x0008		/* 2 Stop bits mask */
#define	SER_1STOP	0x0000		/* 1 Stop bits mask */
#define	SER_TMODE	0x0004		/* TMODE enable mask */
#define	SER_RSIE	0x0002		/* RSIE mask (generate int on err) */
#define	SER_RMODE	0x0001		/* RMODE mask (Rcv interrupt mode) */

/* Serial Port Status Register Definitions */
#define	SPSTS		IOB16B + 0x82	/* Serial Port Status Register */

#define	SER_TEMT	0x0040		/* Transmit Shift Reg Empty mask */
#define	SER_THRE	0x0020		/* Transmit Hold Reg Empty mask */
#define	SER_RDR		0x0010		/* Receive Data Ready mask */
#define	SER_BRKI	0x0008		/* Break Interrupt mask */
#define	SER_FER		0x0004		/* Framing Error mask */
#define	SER_PER		0x0002		/* Parity Error mask */
#define	SER_OER		0x0001		/* Overrun Error mask */

/* Serial Port Transmit Data */
#define	SPTD		IOB16B + 0x84

/* Serial Port Receive Data */
#define	SPRD		IOB16B + 0x86

/* Serial Port Baud Rate Divisor */
#define	SPBAUD	 	IOB16B + 0x88	/* Xtal / (BDIV+1) / 32 = Baud */

/* Define pin modes for serial port */
#define	SER_PIOMODE	0xe7ff
#define	SER_PIODIR	0xe7ff


/* PIO Register Definitions */
#define	PIOMODE0	IOB16B + 0x70	/* PIO 0 Mode Register */
#define	PDIR0		IOB16B + 0x72	/* PIO 0 Direction Register */
#define	PDATA0		IOB16B + 0x74	/* PIO 0 Data Register */
#define	PIOMODE1	IOB16B + 0x76	/* PIO 1 Mode Register */
#define	PDIR1		IOB16B + 0x78	/* PIO 1 Direction Register */
#define	PDATA1		IOB16B + 0x7a	/* PIO 1 Data Register */


/* Timer Register Definitions */
#define	T0CON		IOB16B + 0x56	/* TMR0 Control Register */
#define	T0CMPB	  	IOB16B + 0x54	/* TMR0 Compare-B Register */
#define	T0CMPA		IOB16B + 0x52	/* TMR0 Compare-A Register */
#define	T0CNT		IOB16B + 0x50	/* TMR0 Count Register */

#define	T1CON		IOB16B + 0x5E	/* TMR1 Control Register */
#define	T1CMPB		IOB16B + 0x5C	/* TMR1 Compare-B Register */
#define	T1CMPA		IOB16B + 0x5A	/* TMR1 Compare-A Register */
#define	T1CNT		IOB16B + 0x58	/* TMR1 Count Register */

#define	T2CON		IOB16B + 0x66	/* TMR2 Control Register */
#define	T2CMPA		IOB16B + 0x62	/* TMR2 Compare-A Register */
#define	T2CNT  		IOB16B + 0x60	/* TMR2 Count Register */

/* TxCON register */
#define	TCU_CONT	0x0001		/* Enable continuous mode */
#define	TCU_INT		0x2000		/* Interrupt on terminal count */
#define	TCU_INH		0x4000		/* Permit writes enable bit */
#define	TCU_EN		0x8000		/* Enable bit */


/* Interrupt Control Register Definitions */
#define	SPICON		IOB16B + 0x44	/* Serial Port INT Control Register */
#define	WDCON		IOB16B + 0x42	/* INT 5/WDOG Control Register */
#define	I4CON		IOB16B + 0x40	/* Interrupt 4 Control Register */
#define	I3CON		IOB16B + 0x3E	/* Interrupt 3 Control Register */
#define	I2CON		IOB16B + 0x3C	/* Interrupt 2 Control Register */
#define	I1CON		IOB16B + 0x3A	/* Interrupt 1 Control Register */
#define	I0CON		IOB16B + 0x38	/* Interrupt 0 Control Register */
#define	DMA1CON		IOB16B + 0x36	/* DMA 1 Interrupt Control Register */
#define	DMA0CON		IOB16B + 0x34	/* DMA 0 Interrupt Control Register */
#define	TCUCON		IOB16B + 0x32	/* Timer Interrupt Control Register */
#define INTSTS		IOB16B + 0x30   /* Interrupt Status Register */
#define PRIMSK		IOB16B + 0x2A 	/* Priority MASK Register */
#define IMASK		IOB16B + 0x28 	/* Interrupt MASK Register */

#define	INT_LTM		0x0010		/* Level Trigger Mode mask */
#define	INT_MSK		0x0008		/* Mask Bit mask */
#define	INT_PR2		0x0004		/* Priority Bit PR2 mask */
#define	INT_PR1		0x0002		/*              PR1      */
#define	INT_PR0		0x0001		/*              PR0      */

/* Interrupt Vector Definitions */
#define	SERRX_VEC	20		/* Serial Port Rx Interrupt Vector  */
#define	SERTX_VEC	20		/* Serial Port Tx Interrupt Vector  */
#define	TMR2_VEC	19		/* Timer 2 Interrupt Vector */
#define	TMR1_VEC	18		/* Timer 1 Interrupt Vector */
#define	INT5_VEC	17		/* Interrupt 5 Vector (Watch Dog Timer Interrupt) */
#define	INT4_VEC	16		/* Interrupt 4 Vector */
#define	INT3_VEC	15		/* Interrupt 3 Vector */
#define	INT2_VEC	14		/* Interrupt 2 Vector */
#define	INT1_VEC	13		/* Interrupt 1 Vector */
#define	INT0_VEC	12		/* Interrupt 0 Vector */
#define	DMA1_VEC	11		/* DMA 1 Interrupt Vector */
#define	DMA0_VEC	10		/* DMA 0 Interrupt Vector */
#define	TMR0_VEC	8		/* Timer 0 Interrupt Vector */

/* Interrupt Request Register Definitions */
#define	REQST		IOB16B + 0x2E	/* Interrupt Request Register */

#define	IRR_SPI		0x0400		/* Int Req Reg - SPI Int mask */
#define	IRR_I5 		0x0200		/* Int Req Reg - I5(WDT)Int mask */
#define	IRR_I4 		0x0100		/* Int Req Reg - I4  Int mask */
#define	IRR_I3	 	0x0080		/* Int Req Reg - I3  Int mask */
#define	IRR_I2 		0x0040		/* Int Req Reg - I2  Int mask */
#define	IRR_I1 		0x0020		/* Int Req Reg - I1  Int mask */
#define	IRR_I0	 	0x0010		/* Int Req Reg - I0  Int mask */
#define	IRR_D1 		0x0008		/* Int Req Reg - D1  Int mask */
#define	IRR_D0 		0x0004		/* Int Req Reg - D0  Int mask */
#define	IRR_TMR		0x0001		/* Int Req Reg - TMR Int mask */

/* Interrupt In Service Register Definitions */
#define	INSERV		IOB16B + 0x2C   /* Interrupt In Service Register */

#define	INSERV_SPI	0x0400		/* Int In Serv - SPI Int mask */
#define	INSERV_I5	0x0200		/* Int In Serv - I5(WDT)Int mask */
#define	INSERV_I4	0x0100		/* Int In Serv - I4  Int mask */
#define	INSERV_I3	0x0080		/* Int In Serv - I3  Int mask */
#define	INSERV_I2	0x0040		/* Int In Serv - I2  Int mask */
#define	INSERV_I1	0x0020		/* Int In Serv - I1  Int mask */
#define	INSERV_I0	0x0010		/* Int In Serv - I0  Int mask */
#define	INSERV_D1	0x0008		/* Int In Serv - D1  Int mask */
#define	INSERV_D0	0x0004		/* Int In Serv - D0  Int mask */
#define	INSERV_TMR	0x0001		/* Int In Serv - TMR Int mask */

/* Interrupt Mask Register Definitions */
#define	IMASK		IOB16B + 0x28	/* Interrupt Mask Register */

#define	IMASK_SPI	0x0400		/* Int Mask - SPI mask */
#define	IMASK_VWDT	0x0200		/* Int Mask - VWDT mask */
#define	IMASK_I4	0x0100		/* Int Mask - I4  mask */
#define	IMASK_I3	0x0080		/* Int Mask - I3  mask */
#define	IMASK_I2	0x0040		/* Int Mask - I2  mask */
#define	IMASK_I1	0x0020		/* Int Mask - I1  mask */
#define	IMASK_I0	0x0010		/* Int Mask - I0  mask */
#define	IMASK_D1	0x0008		/* Int Mask - D1  mask */
#define	IMASK_D0	0x0004		/* Int Mask - D0  mask */
#define	IMASK_TMR	0x0001		/* Int Mask - TMR mask */
#define	IMASK_ALL	0x07fd		/* Mask all interrupts */

/* Interrupt Poll Status Register Definitions */
#define	POLLST		IOB16B + 0x26	/* Interrupt Poll Status Register */

/* Interrupt Poll Register Definitions */
#define	POLL		IOB16B + 0x24	/* Interrupt Poll Register */

#define	INTREQ_MASK	0x8000		/* POLL Reg Interrupt Request mask */

/* Interrupt EOI Register Definitions */
#define	EOI		IOB16B + 0x22	/* Interrupt EOI Register */

// ----------------------------------------------
// EOI Type
// ----------------------------------------------
#define EOI_TIMER0	0x08
#define EOI_TIMER1	0x12
#define EOI_TIMER2	0x13

#define EOI_DMA_0	0x0A
#define EOI_DMA_1	0x0B
                 	
#define EOI_INT_0	0x0C
#define EOI_INT_1	0x0D
#define EOI_INT_2	0x0E
#define EOI_INT_3	0x0F
#define EOI_INT_4	0x10

#define EOI_WD		0x11
#define EOI_SERIA	0x14

// ----------------------------------------------
// Maskable Interrupt Type
// ----------------------------------------------
#define TIMER_0_TYPE	0x08
#define TIMER_1_TYPE	0x12
#define TIMER_2_TYPE	0x13

#define DMA_0_TYPE	0x0A
#define DMA_1_TYPE	0x0B
                  	
#define INT_0_TYPE	0x0C
#define INT_1_TYPE	0x0D
#define INT_2_TYPE	0x0E
#define INT_3_TYPE	0x0F
#define INT_4_TYPE	0x10

#define WD_TYPE		0x11
#define SERIAL_TYPE	0x14



#define	NSPEC_MASK	0x8000		/* EOI Reg Non-Specific mask */


/* SSI Status Register Definitions */
#define	SSS		IOB16B + 0x10	/* SSI Status Register */

#define	SSI_RETE	0x0004		/* Rx/Tx Error Detect mask */
#define	SSI_DRDT	0x0002		/* Rx/Tx Complete mask */
#define	SSI_PB		0x0001		/* SSI Ports Busy mask */

/* SSI SDEN Control Register Definitions */
#define	SSC	 	IOB16B + 0x12	/* SSI SDEN Control Register */

#define	SSI_SCLKDIV4	0x0010		/* SSI SCLK Divide by 4 mask */
#define	SSI_DE1		0x0002		/* SSI SDEN1 Enable mask */
#define	SSI_DE0		0x0001		/* SSI SDEN0 Enable mask */

/* SSI Address Register Definition */
#define	SSD1	 	IOB16B + 0x14	/* SSI Address Register */

/* SSI Transmit Data Register Definition */
#define	SSD0		IOB16B + 0x16

/* SSI Receive Data Register Definition */
#define	SSR		IOB16B + 0x18



/*
//
// Calculate the baud rate generator values
//
*/

#if defined(BAUD) && defined(CLK)

#if	!(defined(MSC51) || defined(MSC60))
/* First, compute BAUD rate divisor */
#define DIV0 (CLK/BAUD/32)-1			/* BAUD = CLK/(DIV+1)/32 */
#define DIV1 (DIV0 + 1) 			/* Round up */

/* compute actual baud for both divisors */
#define BAUD0 (CLK/(DIV0+1)/32)
#define BAUD1 (CLK/(DIV1+1)/32)

/* Compare errors and choose better */
#if (BAUD0 - BAUD) < (BAUD - BAUD1)
#define BAUDDIV DIV0
#define RATE_ERR (((BAUD0 - BAUD) * 100) / BAUD)
#else
#define BAUDDIV DIV1
#define RATE_ERR (((BAUD - BAUD1) * 100) / BAUD)
#endif

/* Test that the resulting error is acceptable */
#if	( RATE_ERR > 5 )
#error  Greater than 5% Baudrate error try changing BAUD or CLK.
#endif	/* Baud rate error check */

#else

/* MSC 5.1 and MSC 6.0 can't handle the computation */
/* You must manually determine BAUDDIV and assign it on the next line */
/* use the formula BAUDDIV = (CLK/BAUD/32)-1 */
#define	BAUDDIV	0

#if (BAUDDIV==0)
#error When using MSC 5.1 or MSC 6.0, you must compute BAUDDIV
#endif
#endif /*	!(defined(MSC51) || defined(MSC60)) */

#endif /* defined(BAUD) && defined(CLK) */

#endif	/* _IMS16B_H */